| 56 |
56 |
static puc_config_f puc_config_siig;
|
| 57 |
57 |
static puc_config_f puc_config_timedia;
|
| 58 |
58 |
static puc_config_f puc_config_titan;
|
|
59 |
static puc_config_f puc_config_oxford_pcie;
|
| 59 |
60 |
|
| 60 |
61 |
const struct puc_cfg puc_pci_devices[] = {
|
| 61 |
62 |
|
| ... | ... | |
| 619 |
620 |
* Boards with an Oxford Semiconductor chip.
|
| 620 |
621 |
*
|
| 621 |
622 |
* Oxford Semiconductor provides documentation for their chip at:
|
| 622 |
|
* <URL:http://www.oxsemi.com/products/uarts/index.html>
|
|
623 |
* <URL:http://www.plxtech.com/products/uart/>
|
| 623 |
624 |
*
|
| 624 |
625 |
* As sold by Kouwell <URL:http://www.kouwell.com/>.
|
| 625 |
626 |
* I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
|
| ... | ... | |
| 679 |
680 |
PUC_PORT_4S, 0x10, 0, 8,
|
| 680 |
681 |
},
|
| 681 |
682 |
|
|
683 |
/*
|
|
684 |
* Oxford Semiconductor PCI Express Expresso family
|
|
685 |
*
|
|
686 |
* Found in many 'native' PCI Express serial boards such as:
|
|
687 |
*
|
|
688 |
* eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
|
|
689 |
* <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
|
|
690 |
*
|
|
691 |
* Lindy 51189 (4 port)
|
|
692 |
* <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
|
|
693 |
*
|
|
694 |
* StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
|
|
695 |
* <URL:http://www.startech.com>
|
|
696 |
*/
|
|
697 |
|
|
698 |
{ 0x1415, 0xc158, 0xffff, 0,
|
|
699 |
"Oxford Semiconductor OXPCIe952 UARTs",
|
|
700 |
DEFAULT_RCLK * 0x22,
|
|
701 |
PUC_PORT_NONSTANDARD, 0x10, 0, -1,
|
|
702 |
.config_function = puc_config_oxford_pcie
|
|
703 |
},
|
|
704 |
|
|
705 |
{ 0x1415, 0xc15d, 0xffff, 0,
|
|
706 |
"Oxford Semiconductor OXPCIe952 UARTs (function 1)",
|
|
707 |
DEFAULT_RCLK * 0x22,
|
|
708 |
PUC_PORT_NONSTANDARD, 0x10, 0, -1,
|
|
709 |
.config_function = puc_config_oxford_pcie
|
|
710 |
},
|
|
711 |
|
|
712 |
{ 0x1415, 0xc208, 0xffff, 0,
|
|
713 |
"Oxford Semiconductor OXPCIe954 UARTs",
|
|
714 |
DEFAULT_RCLK * 0x22,
|
|
715 |
PUC_PORT_NONSTANDARD, 0x10, 0, -1,
|
|
716 |
.config_function = puc_config_oxford_pcie
|
|
717 |
},
|
|
718 |
|
|
719 |
{ 0x1415, 0xc20d, 0xffff, 0,
|
|
720 |
"Oxford Semiconductor OXPCIe954 UARTs (function 1)",
|
|
721 |
DEFAULT_RCLK * 0x22,
|
|
722 |
PUC_PORT_NONSTANDARD, 0x10, 0, -1,
|
|
723 |
.config_function = puc_config_oxford_pcie
|
|
724 |
},
|
|
725 |
|
|
726 |
{ 0x1415, 0xc308, 0xffff, 0,
|
|
727 |
"Oxford Semiconductor OXPCIe958 UARTs",
|
|
728 |
DEFAULT_RCLK * 0x22,
|
|
729 |
PUC_PORT_NONSTANDARD, 0x10, 0, -1,
|
|
730 |
.config_function = puc_config_oxford_pcie
|
|
731 |
},
|
|
732 |
|
|
733 |
{ 0x1415, 0xc30d, 0xffff, 0,
|
|
734 |
"Oxford Semiconductor OXPCIe958 UARTs (function 1)",
|
|
735 |
DEFAULT_RCLK * 0x22,
|
|
736 |
PUC_PORT_NONSTANDARD, 0x10, 0, -1,
|
|
737 |
.config_function = puc_config_oxford_pcie
|
|
738 |
},
|
|
739 |
|
| 682 |
740 |
{ 0x14d2, 0x8010, 0xffff, 0,
|
| 683 |
741 |
"VScom PCI-100L",
|
| 684 |
742 |
DEFAULT_RCLK * 8,
|
| ... | ... | |
| 1253 |
1311 |
}
|
| 1254 |
1312 |
|
| 1255 |
1313 |
static int
|
|
1314 |
puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
|
|
1315 |
intptr_t *res)
|
|
1316 |
{
|
|
1317 |
const struct puc_cfg *cfg = sc->sc_cfg;
|
|
1318 |
int idx;
|
|
1319 |
struct puc_bar *bar;
|
|
1320 |
uint8_t value;
|
|
1321 |
|
|
1322 |
switch (cmd) {
|
|
1323 |
case PUC_CFG_SETUP:
|
|
1324 |
device_printf(sc->sc_dev, "%d UARTs detected\n",
|
|
1325 |
sc->sc_nports);
|
|
1326 |
|
|
1327 |
/* Set UARTs to enhanced mode */
|
|
1328 |
bar = puc_get_bar(sc, cfg->rid);
|
|
1329 |
if (bar == NULL)
|
|
1330 |
return (ENXIO);
|
|
1331 |
|
|
1332 |
for (idx = 0; idx < sc->sc_nports; idx++) {
|
|
1333 |
value = bus_read_1(bar->b_res, 0x1000 + (idx << 9)
|
|
1334 |
+ 0x92);
|
|
1335 |
bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
|
|
1336 |
value | 0x10);
|
|
1337 |
}
|
|
1338 |
|
|
1339 |
return (0);
|
|
1340 |
case PUC_CFG_GET_LEN:
|
|
1341 |
*res = 0x200;
|
|
1342 |
return (0);
|
|
1343 |
case PUC_CFG_GET_NPORTS:
|
|
1344 |
/*
|
|
1345 |
* Check if we are being called from puc_bfe_attach()
|
|
1346 |
* or puc_bfe_probe(). If puc_bfe_probe(), we cannot
|
|
1347 |
* puc_get_bar(), so we return a value of 16. This has cosmetic
|
|
1348 |
* side-effects at worst; in PUC_CFG_GET_DESC,
|
|
1349 |
* (int)sc->sc_cfg_data will not contain the true number of
|
|
1350 |
* ports in PUC_CFG_GET_DESC, but we are not implementing that
|
|
1351 |
* call for this device family anyway.
|
|
1352 |
*
|
|
1353 |
* The check is for initialisation of sc->sc_bar[idx], which is
|
|
1354 |
* only done in puc_bfe_attach().
|
|
1355 |
*/
|
|
1356 |
idx = 0;
|
|
1357 |
do {
|
|
1358 |
if (sc->sc_bar[idx++].b_rid != -1) {
|
|
1359 |
sc->sc_cfg_data = 16;
|
|
1360 |
*res = sc->sc_cfg_data;
|
|
1361 |
return (0);
|
|
1362 |
}
|
|
1363 |
} while (idx < PUC_PCI_BARS);
|
|
1364 |
|
|
1365 |
bar = puc_get_bar(sc, cfg->rid);
|
|
1366 |
if (bar == NULL)
|
|
1367 |
return (ENXIO);
|
|
1368 |
|
|
1369 |
value = bus_read_1(bar->b_res, 0x04);
|
|
1370 |
if (value == 0)
|
|
1371 |
return (ENXIO);
|
|
1372 |
|
|
1373 |
sc->sc_cfg_data = value;
|
|
1374 |
*res = sc->sc_cfg_data;
|
|
1375 |
return (0);
|
|
1376 |
case PUC_CFG_GET_OFS:
|
|
1377 |
*res = 0x1000 + (port << 9);
|
|
1378 |
return (0);
|
|
1379 |
case PUC_CFG_GET_TYPE:
|
|
1380 |
*res = PUC_TYPE_SERIAL;
|
|
1381 |
return (0);
|
|
1382 |
default:
|
|
1383 |
break;
|
|
1384 |
}
|
|
1385 |
return (ENXIO);
|
|
1386 |
}
|
|
1387 |
|
|
1388 |
static int
|
| 1256 |
1389 |
puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
|
| 1257 |
1390 |
intptr_t *res)
|
| 1258 |
1391 |
{
|